1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device including a static random access memory (SRAM) and a method of fabricating the same.
2. Description of Related Art
An SRAM is one type of semiconductor memory device and does not need refreshing. Therefore, the SRAM enables system configuration to be simplified and consumes only a small amount of current in await mode. Because of this, the SRAM is suitably used as a memory for portable devices such as a portable telephone in which the number of parts is limited and the power consumption therefor is required to be small.
The SRAM generally stores information using a flip-flop formed of two inverters, each having a load transistor and a driver transistor. The flip-flop is formed by connecting the gate electrode of one inverter to the drain of the other inverter. Specifically, the flip-flop is formed by cross-coupling one inverter with the other.
At present, miniaturization of portable devices is strongly demanded. As a means to achieve such a demand, miniaturization of memory cells of the SRAM has been demanded. For example, miniaturization of an SRAM by forming a flip-flop using two layers has been attempted.
In the case of forming a flip-flop using two layers, a layer for connecting the drains of each inverters and a layer for connecting the drain and the gate of the inverter can be cross-coupled by forming these layers as one conductive layer. According to this structure, such a conductive layer is formed over the regions including a region in which the drain of one inverter is formed, a region in which the gate of the other inverter is formed, and a region which connects these regions. Therefore, the conductive layer has a pattern with three ends (for example, a pattern having a branched portion in the shape of the letters xe2x80x9cTxe2x80x9d or xe2x80x9chxe2x80x9d), or a spiral pattern in which the arms are intricate. For example, a pattern having a branched portion in the shape of the letter xe2x80x9cTxe2x80x9d is disclosed by Japanese Patent Application Laid-open No. 10-41409 in FIG. 1. A pattern with a branched portion in the shape of the letter xe2x80x9cTxe2x80x9d is also disclosed by M. Ishida, et. al. in International Electron Devices Meeting Technical Digest, 1998, page 203, FIG. 4(b). An example of a spiral pattern also can be seen in this International Electron Devices Meeting Technical Digest, page 203, FIG. 3(b).
However, in the case of SRAMs having such patterns, since the flip-flop is formed using two layers, the patterns of each layer are complicated. Therefore, it is difficult to reproduce the shape of a minute pattern in a photoetching step with high accuracy, whereby a desired pattern cannot be obtained. This hinders miniaturization of the memory size.
An objective of the present invention is to provide a semiconductor device having memory cells with a reduced size.
Another objective of the present invention is to provide a method of fabricating a more miniaturized semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a memory cell portion having memory cells each of which includes two load transistors, two driver transistors, and two access transistors; and
a peripheral circuit portion which includes MOS transistors, wherein:
each of the memory cells includes first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers;
the first and second gate-gate connecting layers are formed over a semiconductor substrate;
the first and second drain-drain connecting layers are formed over a first interlayer dielectric and connect drains of the load transistors with drains of the driver transistors;
the first and second drain-gate connecting layers are formed over a second interlayer dielectric;
the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate-gate connecting layer;
the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate-gate connecting layer;
the first and second gate-gate connecting layers, the first and second drain-drain connecting layers, and the first and second drain-gate connecting layers are provided in different layers at different levels;
the peripheral circuit portion has the first interlayer dielectric, the second interlayer dielectric, and a first wiring layer formed over the second interlayer dielectric; and
the first and second drain-gate connecting layers and the first wiring layer are formed in a layer at the same level.
The peripheral circuit portion includes circuits and others which are formed around the memory cell portion, for controlling or driving the memory cell portion or for operating with the memory cell. As examples of the peripheral circuit portion, an address decoder, sense amplifier, address buffer, control circuit, microcomputers such as an MCU or MPU, and the like can be given.
According to the semiconductor device of the present invention, the first and second gate-gate connecting layers are formed over the semiconductor substrate, the first and second drain-drain connecting layers are formed over the first interlayer dielectric, and the first and second drain-gate connecting layers are formed over the second interlayer dielectric, wherein a flip-flop is formed in the memory cell by these three layers. Therefore, the patterns of these layers can be simplified in comparison with a case of forming a flip-flop using two layers, thereby achieving miniaturization of the semiconductor device.
In the present invention, the term xe2x80x9cformed in a layer at the same levelxe2x80x9d mainly means that the layers are formed in the same step. According to this configuration, the drain-gate connecting layers and the first wiring layer are formed in a layer at the same level in the same step, thereby reducing production costs.
Each of the memory cells may include an upper wiring layer formed over a third interlayer dielectric; the peripheral circuit portion may include the third interlayer and a second wiring layer formed over the third interlayer dielectric; and the upper wiring layer and the second wiring layer may be formed in a layer at the same level. This configuration can further increase the above effects. In this case, the upper wiring layer may be used as a bitline wiring layer.
The semiconductor device of the present invention has modifications as follows.
(1) Each of the first and second drain-drain connecting layers may have a thickness of 50-200 nm and a sheet resistance of 50 xcexa9/xe2x96xa1 or less. According to this configuration, a drain-drain connecting layer having a thickness and resistance appropriate to the use of the device can be obtained. If the drain-drain connecting layers have the above thickness, the focus margin can be increased when patterning the drain-drain connecting layers. This increases the wiring density and yield of the drain-drain connecting layers.
(2) The semiconductor memory device may further comprise first contact portions formed in the first interlayer dielectric, second contact portions formed in the second interlayer dielectric, and third contact portions formed through the first interlayer dielectric and second interlayer dielectric. If there are provided the third contact portions, it is not necessary to form connecting layers which connect the first contact portions to the second contact portions. Therefore, in a minute region, a degree of freedom relating to the location of the contact portions can be ensured by forming the third contact portions, thereby enabling the memory size to be reduced.
In this modification, the first and second gate-gate connecting layers may be connected to the first and second drain-drain connecting layers by the first contact portions.
Moreover, the first and second gate-gate connecting layers may be connected to the first and second drain-gate connecting layers by the third contact portions.
In this modification, first contact pad layers may be formed in the same step of forming the first and second drain-drain connecting layers and used to connect the upper wiring layer to source/drain regions of the access transistors. The second contact portions may be formed over the first contact portions with the first contact pad layers interposed.
The contact pad layer is a conductive layer formed between two contact portions stacked in the direction perpendicular to the surface of the semiconductor substrate over which the transistors are formed. According to this configuration, the second contact portions can be securely connected to the first contact portions.
In this case, the second contact portions may be formed over the first and second drain-drain connecting layers and connect the first and second drain-drain connecting layers to the first and second drain-gate connecting layers.
Contact holes in the third contact portions may have an aspect ratio of preferably 6 or less, and still more preferably 5 or less. The aspect ratio is the ratio of the depth of a contact hole to the lower end diameter of the contact hole. According to this configuration, opening can be formed securely in contact portions with a small diameter, whereby the drain-drain connecting layers can be connected to the drain-gate connecting layers.
(3) Each of the first and second drain-drain connecting layers may include a refractory metal nitride layer. According to this configuration, a thinner layer can be formed whereby processing with higher accuracy can be ensured. Such a thinner layer increases the focus margin when patterning the layer due to small difference in the steps, thereby increasing the wiring density and yield of the drain-drain connecting layers.
In this case, each of the first and second drain-drain connecting layers may further include a refractory metal layer. According to this configuration, the drain-drain connecting layers can be provided with lower resistance, and the thickness thereof can be decreased.
(4) An insulating layer containing silicon nitride and silicon oxide may be formed over the semiconductor substrate. According to this configuration, effects caused by the deviation of the positions of the first contact portions formed over the semiconductor substrate can be decreased for reasons to be described later.
(5) The distance between the semiconductor substrate and the first and second drain-drain connecting layers may be preferably 300 to 1000 nm, and still more preferably 600 to 800 nm. The distance between the first and second drain-drain connecting layers and the first and second drain-gate connecting layers may be preferably 200 to 600 nm, and still more preferably 300 to 500 nm. The distance between the semiconductor substrate and the first and second drain-gate connecting layers may be preferably 1400 nm or less. According to this configuration, the memory cell can be miniaturized.
The semiconductor device of the present invention may further comprise other circuit regions. In this case, the other circuit regions may include a logic circuit. A memory circuit such as a flash memory, cell base circuit, or ROM, a reduced instruction set computer (RISC), intellectual property (IP) macro, an analog circuit and the like can be given as examples. According to this configuration, isolation regions, gate insulating layers, gate electrodes, interlayer dielectrics, wiring layers and the like in the other circuit regions can be formed in the same step of forming the memory cell portion, thereby reducing the number of fabrication steps.
According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device in which a memory cell portion having memory cells each of which includes two load transistors, two driver transistors and two access transistors, and a peripheral circuit portion which includes MOS transistors are respectively formed in predetermined regions of a semiconductor substrate, the method comprising the steps of:
(a) forming a gate-gate connecting layer over the semiconductor substrate within a region of the memory cells and forming a gate electrode layer over the semiconductor substrate within a region of the peripheral circuit portion;
(b) forming a first interlayer dielectric over the semiconductor substrate within a region of the gate electrode layer and the gate-gate connecting layer;
(c) forming a drain-drain connecting layer over part of the first interlayer dielectric within a region of the memory cells;
(d) forming a second interlayer dielectric over the first interlayer dielectric; and
(e) forming a drain-gate connecting layer over the second interlayer dielectric within a region of the memory cells and forming a first wiring layer over the second interlayer dielectric within a region of the peripheral circuit portion.
According to this method of fabricating a semiconductor device, circuits having different functions can be fabricated in a further miniaturized semiconductor device with high accuracy. Moreover, a semiconductor device can be fabricated at high yield.
The method of fabricating a semiconductor device of the present invention has modifications as follows.
(1) The method may further comprise the steps of:
(f) forming a third interlayer dielectric over the second interlayer dielectric; and
(g) forming an upper wiring layer over the third interlayer dielectric within a region of the memory cells, and forming a second wiring layer over the third interlayer dielectric within a region of the peripheral circuit portion.
According to this method, the drain-gate connecting layers of the memory cell and the first wiring layer in the peripheral circuit portion can be formed in the same step, and the upper wiring layer of the memory cell and the second wiring layer in the peripheral circuit portion can be formed in the same step. Therefore, the number of steps can be decreased, thereby reducing production costs.
(2) An insulating layer containing silicon nitride and silicon oxide may be formed over the semiconductor substrate after the step (a).
(3) The method may further comprise the steps of:
(h) forming first contact portions in the first interlayer dielectric;
(i) forming third contact portions through the first interlayer dielectric and the second interlayer dielectric; and
(j) forming second contact portions in the second interlayer dielectric.
According to this method of fabricating a semiconductor device, a semiconductor device having miniaturized memory cells can be fabricated with high accuracy.
In this case, first contact pad layers which connect the first contact portions to the second contact portions may be formed over the first interlayer dielectric together with the first and second drain-drain connecting layers in the step (c).